Generally, a conventional GaAs FET includes a semi-insulating GaAs substrate as thin as several tens of microns and a PHS disposed on the rear surface of the substrate to reduce the thermal resistance of the device.
FIG. 14 is a perspective view illustrating a conventional semiconductor chip including a semiconductor substrate 2 about 35 .mu.m thick and a PHS 1 about 35 .mu.m thick.
FIG. 15 is a bottom plan view schematically illustrating a wafer before being divided into a plurality of semiconductor chips, and FIG. 16 is a sectional view taken along line I--I of FIG. 15. In these figures, reference numeral 7 designates a semiconductor wafer having opposite front and rear surfaces. A plurality of semiconductor devices, such as FETs, are disposed in a surface region of the wafer 7. A PHS 1 is disposed on the rear surface of the wafer 7 opposite each of the semiconductor devices 3. The diameter of the wafer 7 is about 3 inches and the thickness of the wafer 7 with the PHS 1 is about 35 .mu.m. A photoresist film 8 is disposed on the front surface of the wafer 7 to protect the semiconductor devices. A glass plate 5 is attached to the photoresist film 8 via a wax 9. Reference numeral 6 designates an orientation flat, i.e., a reference line showing the crystal orientation of the wafer 7.
FIGS. 17(a) to 17(e) are sectional views illustrating process steps for producing the PHS 1 of FIG. 16.
Initially, as illustrated in FIG. 17(a), the photoresist film 8 is deposited on the front surface of the wafer 7, and the wafer is adhered to the glass plate 5 using the wax 9. Then, a photoresist film 10, 40 .mu.m, thick is deposited over the rear surface of the wafer 7 (FIG. 17(b)) and patterned by conventional photolithography (FIG. 17(c)). Using the photoresist pattern 11 as a mask, a metal, such as Au, is selectively deposited by electroplating (FIG. 17(d), followed by removal of the photoresist pattern 11, forming a plurality of Au PHS layers (rear electrodes) 1 (FIG. 17(e)). Each of the PHS layers 1 is 35 .mu.m thick and 1 mm.times.2.about.3 mm in size.
FIG. 18 is a sectional view illustrating a process step of dividing the wafer 7 into a plurality of semiconductor chips. In FIG. 18, the wafer 7 is selectively etched by wet etching using the PHS layers 1 as a mask to divide the wafer 7 into a plurality of semiconductor chips 2. Thereafter, the photoresist film 8 and the wax 9 are melted and removed using chemicals, whereby the respective semiconductor chips 2 are separated from the glass plate 5, resulting in the semiconductor chip 2 with the PHS 1 shown in FIG. 14. Since the wet etching is isotropic, the semiconductor substrate 2 is smaller than the PHS 1.
In the conventional production process, since the semiconductor devices 3 are disposed in the surface region of the wafer 7 and the PHS layers 1 are disposed on the rear surface of the wafer 7 opposite the respective semiconductor devices, the electrical testing of the semiconductor devices have to be carried out after the formation of the PHS layers 1. However, since the wafer 7 is thinned to about 35 .mu.m by polishing the rear surface thereof before the formation of the PHS layers 1 to improve the heat radiation, the glass plate 5 is used to support the thin wafer 7.
That is, the wafer 7 has to be attached to the glass plate 5 until the wet etching process for dividing the wafer into individual chips is finished and, therefore, the electrical testing of the semiconductor chips is carried out after separating the chips from the glass plate 5. Since each of the semiconductor chips is handled with tweezers, the electrical testing takes a lot of time and the semiconductor chip may be cracked due to the tweezers.